Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
In a conventional flipchip type package, a semiconductor die is mounted to a package substrate with the active side of the die facing the substrate. The substrate contains a dielectric layer and metal layers, patterned to provide substrate circuitry, which includes among other features traces or leads routed to interconnect pads. The metal layer can be patterned by a mask and etch process. The interconnection of the circuitry in the semiconductor die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding complementary array of interconnect pads or capture pads on the substrate. The capture pads are typically about 2 to 4 times the nominal or design width of the leads. The interconnect area on the capture pad is approximately equal to the interconnect area on the die pad.
The areal density of electronic features on integrated circuits has increased enormously, and a semiconductor die having a greater density of circuit features also may have a greater density of sites for interconnection with the package substrate.
The package is connected to underlying circuitry, such as a printed circuit board or motherboard, by way of second level interconnects between the package and underlying circuit. The second level interconnects have a greater pitch than the flipchip interconnects so the routing on the substrate conventionally fans out. Significant technological advances have enabled construction of fine lines and spaces. In the conventional arrangement, space between adjacent pads limits the number of traces than can escape from the more inward capture pads in the array. The fan-out routing between the capture pads beneath the semiconductor die and external pins of the package is formed on multiple metal layers within the package substrate. For a complex interconnect array, substrates having multiple layers can be required to achieve routing between the die pads and second level interconnects on the package.
Multiple layer substrates are expensive and, in conventional flipchip constructs, the substrate alone typically accounts for more than half the package cost. The high cost of multilayer substrates has been a factor in limiting proliferation of flipchip technology in mainstream products. The escape routing pattern typically introduces additional electrical parasitics because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.
The conventional flipchip interconnection is made by using a melting process to join the bumps onto corresponding interconnect sites on the patterned metal layer at the die attach surface of the substrate. Where the site is a capture pad, the interconnect is known as a bump-on-capture pad (BOC) interconnect. In the BOC design, a comparatively large capture pad is required to mate with the bump on the semiconductor die. In some flipchip interconnections, an insulating material or solder mask is required to confine the flow of solder during the interconnection process. The solder mask opening defines the contour of the melted solder at the capture pad, i.e., solder mask defined, or the solder contour may not be defined by the mask opening, i.e., non-solder mask defined. In the latter case, the solder mask opening is significantly larger than the capture pad. Since the techniques for defining solder mask openings have wide tolerance ranges for a solder mask defined bump configuration, the capture pad must be large, typically considerably larger than the design size for the mask opening, to ensure that the mask opening will be located on the mating surface of the pad. The larger width of the capture pads results in considerable loss of routing space on the top substrate layer. In particular, the escape routing pitch is much larger than the finest trace pitch that the substrate technology can offer. A significant number of pads must be routed on lower substrate layers by means of short stubs and vias, often beneath the footprint of the die, emanating from the pads in question.
FIG. 1a shows a portion of a conventional flipchip package, in diagrammatic sectional view taken in a plane perpendicular to the package substrate surface. A die attach surface of package substrate 10 includes a patterned electrically conductive layer formed on a dielectric layer. The conductive layer is patterned to form leads and capture pads 16. An insulating layer or masking layer 11 covers the die attach surface of substrate 10. Masking layer 11 is a photo-definable material patterned with photoresist to have mask openings 12 which expose the mating surfaces of capture pads 16. Bumps 17 attached to under bump metallization (UBM) 18 on the active side of semiconductor die 14 are joined to the corresponding capture pads 16 on substrate 10 to form appropriate electrical interconnection between the circuitry on the die and leads on the substrate. The active side of semiconductor die 14 is covered, except at the contact surfaces of UBM 18, with a passivation layer 15, such as polyimide. After the reflowed solder is cooled to establish the electrical connection, an underfill material 20 is introduced into the space between semiconductor die 14 and substrate 10 to mechanically stabilize the interconnect and protect the features between the die and the substrate.
In such a conventional flipchip interconnect arrangement, signal escape traces in the upper metal layer of the substrate are routed from their respective capture pads across the die edge location, and away from the die footprint. Capture pads 16 are typically much larger than the trace width. For example, capture pads 16 are arranged in a 210 micrometer (μm) two-row area array pitch in a masking layer defined configuration with one signal trace between adjacent capture pads in the marginal row. The effective escape pitch is 105 μm. The escape pitch is adequate to route a significant proportion of integrated circuit designs that commonly employ flipchip interconnection on a single metallization layer, based on the inherent input/output (I/O) density of the IC device architectures.
FIG. 1a shows a masking layer defined solder contour. As the fusible material of the bumps on the die melts, the molten solder tends to wet the metal of the capture pads, and the solder tends to run out over any contiguous metal surfaces that are not masked. The solder tends to flow along the underlying pad and exposed contiguous lead. In a masking layer defined contour, the solder flow is limited by the masking layer, i.e., the width of mask opening 12. In a non-masking layer defined solder contour, the flow of solder along the lead is limited at least in part by a patterned deposition of non-solder-wettable material on the lead surface.
A thermal-induced movement in the x-y plane of die pads on the die attach surface of semiconductor die 14 in relation to the corresponding points on substrate 10, as indicated by arrow 13, can result in stresses to the interconnections between the die pad and interconnect site on the substrate. Various temperature-induced dimensional changes between semiconductor die 14 and substrate 10 are shown in the plan view in FIG. 1b. If there is a significant mismatch between the coefficient of thermal expansion (CTE) of semiconductor die 14 and the CTE of substrate 10, then the die is subject to movement, as shown by arrows 22, relative to the substrate in the x-y plane parallel to the plane of the substrate as the temperature changes, e.g., during thermal cycling in assembly or test or die burnout routines. For example, assume semiconductor die 14 has a footprint occupying area 24a at a low temperature. At higher temperatures, the footprint of semiconductor die 14 expands to area 24b. 
In addition, movement in the x-y plane of a die pad in relation to an underlying contact pad can result in stresses to the interconnection between the pad and the contact pad. The relative movement between semiconductor die 14 and substrate 10 asserts stress on bumps 17, which can cause bump detachment and device failure, particularly at location 26 between the bump and die pad.